As a large capacity nonvolatile memory, instead of a floating gate type NAND flash memory in the related art, a development of a two-terminal resistive random access memory has been actively conducted. In this type of memory, a low voltage⋅low current operation, a high speed switching, or a miniaturization and high integration of memory cells is possible.
In a large capacity memory array, a large number of metal wirings called bit lines and word lines are arranged in an intersecting manner, and a memory cell is formed at an intersection of a bit line and a word line. Writing in one memory cell is performed by applying a voltage to the bit line BL and the word line WL connected to the cell.
In the large capacity memory cell array described above, in order to reduce a chip area, it is preferable to drive as many word lines as possible using as few word line driver circuits as possible and as few decoder circuits as possible. However, when many word lines are connected to one word line driver circuit, non-selected current also flows in a non-selected memory cell. Therefore, as a result, a word line driver circuit is required which allows a large current to flow and has a large chip area, and thus there is a problem that the chip area becomes even larger than before.
Further, in a case of connecting many word lines to one word line driver circuit, for example, it is preferable to provide a decoder circuit that determines the layer to which the word line to be selected belongs, and a decoder circuit that determines the word line in that layer to be selected. However, in this case, the number of the decoder circuits and the number of the wirings for driving the decoder circuit become too large, which leads to a problem that the chip area becomes even larger than before.
Examples of related art include US-A-2017/0200676.